1. Technical Field
The present invention relates to a flash cell fuse circuit and method of fusing a flash cell, and more particularly to a flash cell fuse circuit and fusing method for preventing cells coupled to a common bit line from being simultaneously activated.
2. Discussion of the Related Art
A flash cell refers to a semiconductor element that is capable of selectively passing or intercepting an electric current. The flash cell may be used as a fuse since it is a nonvolatile element that does not need power to maintain data stored therein. As a result, the flash cell is increasingly being used in place of a conventional metal fuse.
This is so because when a conventional metal fuse is used to store data, the metal fuse has to be cut by using a laser and once the metal fuse is cut it cannot be repaired. Thus, because a flash cell fuse circuit does not require the same procedures for storing data, the flash cell fuse circuit may be provided at a relatively lower cost and may be easier to test than the conventional metal fuse.
FIG. 1 is a circuit diagram illustrating a conventional flash cell fuse circuit. Referring to FIG. 1, the flash cell fuse circuit includes a fuse cell array 100 and fuse sense amplifiers 200 and 300. The fuse cell array 100 includes a first fuse cell array 110 controlled by a first word line W1 and a second fuse cell array 120 controlled by a second word line W2. The first fuse cell array 110 and the second fuse cell array 120 may be used for fusing tasks that are different from each other.
The first fuse cell array 110 includes flash cells C00 and C01 and the second fuse cell array 120 includes flash cells C10 and C11. The flash cells C00 and C10 are coupled to a first bit line B1 and flash cells C01 and C11 are coupled to a second bit line B2. The flash cells C00 and C01 are connected to a source line S1 and the flash cells C10 and C11 are connected to a source line S2. The source lines S1 and S2 are typically connected to ground.
When reading flash cell data that is recorded by a program operation or an erase operation, the flash cells C00 and C01 are activated when the first word line W1 is activated. Data of the flash cell C00 is transferred to the first bit line B1 and output as a first output voltage F01 through the first fuse sense amplifier 200. Data of the flash cell C01 is transferred to the second bit line B2 and output as a second output voltage F02 through the second fuse sense amplifier 300.
In the same way, the flash cells C10 and C11 are activated when the second word line W2 is activated. Data of the flash cell C10 is transferred to the first bit line B1 and output as the first output voltage F01 through the first fuse sense amplifier 200. Data of the flash cell C11 is transferred to the second bit line B2 and output as the second output voltage F02 through the second fuse sense amplifier 300. The output voltages F01 and F02 are then applied to respective gates in a circuit block that needs to be fused, thus completing a fusing procedure.
When fuse cells have a configuration in which a word line and a source line are separated while a bit line is shared as shown in FIG. 1, a program operation and an erase operation may be executed separately. In addition, when the bit line is shared, the flash cell fuse circuit may be easily tested, and an integration density of the layout of a flash cell array may be enhanced as compared to a flash cell fuse circuit that has a separated bit line.
However, in the flash cell fuse circuit illustrated in FIG. 1, a flash cell may be inadvertently activated, thus unwanted data may be transferred to the bit line and then output through the fuse sense amplifier. For example, when word line enable signals, which activate the word lines W1 and W2, are simultaneously enabled, the data of the flash cells C00 and C10 are transferred to the bit line B1 at the same time. Thus, if the word line W2 is inadvertently activated, unwanted data may be transferred to the bit line B1 and output as the first output voltage F01 instead of the data of the flash cell C00.
Therefore, a need exists for a flash cell fuse circuit that is capable of preventing flash cells coupled to a common bit line from being simultaneously activated.